In communication systems, frequency synthesizers can be used for frequency conversion. Recently, all-digital implementations of phase-locked loop (PLL) circuits (for example to realize frequency synthesizers) have gained a lot of attention. Examples of such all-digital implementations are described for example in R. B. Staszewski et al, “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS”, IEEE Journal of Solid-State Circuits, December 2004, and N. Da Dalt et al, “A Compact Triple-Band Low-Jitter Digital LC PLL With Programmable Coil in 130-nm CMOS”, IEEE Journal of Solid-State Circuits, July 2005. In such a PLL, the phase detector is a digital building block, i.e., its output signal is available as a time and amplitude discrete quantity, which allows use of a digital loop filter. This has several benefits, such as lower loop filter area (i.e. lower chip cost), simplified portability to newer technologies, flexibility of PLL bandwidth, faster lock times and possibly output spectral accuracy improvement.
FIG. 2 shows a general block diagram of an example of an all-digital PLL circuit. A digitally controlled oscillator (DCO) 70 outputs a desired frequency N*Fref which is the N-fold of an input reference frequency Fref. A digital loop filter 60 clocked by the reference frequency Fref generates frequency control words for the DCO 70.
In order to be able to use a simple phase detector (such as a bang-bang phase detector), some form of frequency detection is needed to avoid locking to the wrong output frequency. This is provided by the counters 20, 32 in FIG. 2. A high speed +1-counter 32 is clocked by the DCO output N*Fref and is actually used as a phase detector with a range larger than ±360 degrees (the actual range depends on the number of bits in the counter), also known as a phase accumulator. Because the accumulator only changes value due to the oscillator edges, the phase accumulator has a quantization error that can range between ±1 oscillator period. The output of the +1-counter 32 is sampled by a register 40 at the lower reference frequency Fref and subtracted from an output of a +N-counter 20 which has a quantization step corresponding to N oscillator periods and is clocked by the reference frequency Fref. Together with the phase detector (PD) 10 accurate phase lock can be achieved (due to the fine phase detection operation at the PD 10) at the correct frequency (due to the phase accumulator, i.e. the +1-counter 32).
However, when trying to use the +1-counter 32 at high input (oscillator) frequencies NFref, a problem is encountered. If a synchronous +1-counter 32 is used (i.e. all internal flip-flops are clocked by the oscillator frequency NFref), which has enough bits to guarantee locking to the correct frequency, long internal loops exist to handle the internal carry signals, which limit the operation speed. Also, the power consumption of such a counter tends to be high.
On the other hand, if an asynchronous counter topology (where all internal flip-flops change state at different moments in time, e.g., in a ripple counter) is used to overcome these problems, another problem is faced. Because the PLL reference signal samples the complete counter output as one single value at a certain moment in time, the first flip-flops in the asynchronous counter may have already changed value, while others did not do so yet, due to internal flip-flop delays, thus causing a completely wrong value to be read out of the counter and causing the PLL to be controlled in the wrong direction. In the following, this phenomenon is called a “glitch”.
FIG. 3 shows a schematic block diagram of an asynchronous 3-bit counter (i.e. 3-bit ripple counter) consisting of three toggle flip-flop circuits 320-322 that change their state (i.e. toggle) at each falling edge of their input clock. Of course, the flip-flop circuits could as well be designed to change state at the rising edge. An oscillator frequency Fosc is supplied to a clock input of the first flip-flop circuit 320. Due to the asynchronous nature of this counter, the output S0 of the first flip-flop circuit 320 is supplied to a clock input of the second flip-flop circuit 321 and the output S1 of the second flip-flop circuit is supplied to a clock input of the third flip-flop circuit 322 with an output S2.
FIG. 4 shows a state diagram that illustrates the above-mentioned glitch problem in such asynchronous counter topologies. Each row in this schematic table indicates the state of the different sections (i.e. toggle flip-flops 320-322 in this case), the upper row represents the state or output S0 of fastest running flip-flop circuit 320 (which can be seen as a 1-bit counter), the row below indicates the state or output S1 of the counter clocked by the fastest and so on. The small and short vertical lines indicate the switching instances of each particular section or counter stage (i.e. flip-flop circuit), where the delay of the counter stages is shown by the fact that the vertical lines occur at different time instances for each counter stage. The bold and long vertical lines depict sampling instances (examples) and clarify the glitch problem, caused by internal delays. In the present example, the last binary output sample should have been “000” (in the absence of any delays), but in fact the last counting section (i.e. flip-flop circuit 322) did not toggle yet, resulting in an erroneous output sample “100” that cannot be detected in principle. There is no way of knowing that the counter was not in fact supposed to be in the state “100”.
Using a frequency divider between the oscillator and the counter (thus reducing the input frequency of the counter) does not solve this glitch problem in a satisfactory manner, because the lowered frequency increases the quantization error of the accumulator-based phase detector of FIG. 2 and, with that, the PLL lock time may be increased. The PLL reacts most accurately to errors if they are most accurately measured.